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Part Manufacturer Description PDF & SAMPLES
LM4308SQ/NOPB Texas Instruments Mobile Pixel Link Two (MPL-2) - 18-bit CPU Display Interface Master/Slave 40-WQFN -40 to 85
CD4027BM96E4 Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-SOIC -55 to 125
M/05102BEA Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125
CD4027BF3AS2534 Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP
JM38510/05102BEA Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125
CD4027BMT Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-SOIC -55 to 125

"1 wire slave interface" verilog

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: fully PCI-compliant Master/Slave interface, implemented in a single QuickLogic QL2009 FPGA. It utilizes , space and are accessed using slave mode. The Peripheral Component Interconnect (PCI) is a , Complete Test Harness · Simplifies Debugging · Dummy Master Block · Dummy Slave Block · , the schematics and Verilog source code. 4.1 External Interface Signals Figure 4 indicates the , to be implemented. When enabled by the system, PERR# is driven during a Slave bus cycle two clocks QuickLogic
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80C300 16 byte register VERILOG pci master verilog code design of dma controller using vhdl AN21 verilog code of 8 bit comparator QAN15
Abstract: fully PCI-compliant Master/Slave interface, implemented in a single QuickLogic QL24x32B FPGA. It , space and are accessed using slave mode. QAN15 In addition to its high-speed bus definition, PCI , Slave Block · Data Capture and Protocol Checking Please note that Low True signals are , Verilog source code. Figure 4 indicates the external signals of the FPGA, connecting to the PCI Bus and , parity-generation and detection to be implemented. When enabled by the system, PERR# is driven during a Slave bus -
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vhdl code for 4 channel dma controller pin vga CRT pinout pci schematics QL24X32B pc motherboard schematics digital clock verilog code
Abstract: MSB 16 Starting MSB 16 Creating a Platform Description in MSB 18 Connecting Master and Slave Ports , Creating the Verilog Wrapper for VHDL Designs Pointing to the Correct .ngo File 92 90 Making Custom , . LatticeMico32 Slave Passthrough, which describes the features and functionality of the LatticeMico32 slave , microprocessor. You do not add your source HDL at this point, because your Verilog or VHDL source will be , . The following types are currently supported for LatticeMico32 platforms: Verilog HDL Mixed Verilog -
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experiment project ips Future scope of UART using Verilog LatticeMico32 vhdl spi interface wishbone EDN handbook lattice wrapper verilog with vhdl
Abstract: controller and driver are able to display a wide variety of symbols through the interpretation of a simple 4-wire interface. The 4-wire interface includes the following signals: · Read/write enable (E) · Register select , consists of three modules, the top-level module, the WISHBONE slave module and the LCD interface module , ] wb_adr_i[7:0] wb_dat_i[7:0] wb_dat_o[7:0] wb_stb_i wb_we_i lcd_con.v WISHBONE Slave Module , design. WISHBONE Slave Module The WISHBONE slave module interprets write/read commands from the Lattice Semiconductor
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LCMXO2-1200HC-4TG100C LCMXO2280C-3T100C LFXP2-5E-5TN144C LCD module in VHDL lcd module verilog vhdl for lcd wishbone RD1053 1-800-LATTICE
Abstract: PSoC® CreatorTM Component Data Sheet Serial Peripheral Interface (SPI) Slave 2.0 Features · · · 2 to 16-bit data width 4 SPI modes Data rates to 33 Mb/s General Description The SPI Slave provides an industry-standard 4-wire slave SPI interface and 3-wire (or bidirectional) SPI mode. The , standard 8-bit interface, the SPI Slave supports a configurable 2- to 16-bit interface for interfacing to nonstandard SPI word lengths. SPI signals include the standard SCLK, MISO + MOSI (or SDAT) pins and Slave Cypress Semiconductor
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0x2228 aardvark i2c 0x2222 0x2227 aardvark spi BUFFER FIFO
Abstract: signal integrity. · Fast prototyping ability. · Synthesizability (verilog code). · Low cost. · Ease , into two major blocks: Each processor can be a master or a slave in a particular configuration while both RAMs have a slave role at all times. When the Motorola 68040 is the master, either of the SBUS devices or both can be a slave. When either of the SBUS devices is the master, only the 68040 can be the slave and the other SBUS device is idle. · Data Path. The chip controlling the Actel
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A1460-1 n627 N639 A1460 N641 N637 n634 A1460A-1
Abstract: integrity. · Fast prototyping ability. · Synthesizability (verilog code). · Low cost. · Ease of debugging , device, determining the slave device, controlling data transmission, and checking and correcting any , be a master or a slave in a particular configuration while both RAMs have a slave role at all times. When the Motorola 68040 is the master, either of the SBUS devices or both can be a slave. When either of the SBUS devices is the master, only the 68040 can be the slave and the other SBUS device is idle Actel
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N642 N629 68040 verilog model n633 n636 n628
Abstract: integrity. · Fast prototyping ability. · Synthesizability (verilog code). · Low cost. · Ease of , two major blocks: Each processor can be a master or a slave in a particular configuration while both RAMs have a slave role at all times. When the Motorola 68040 is the master, either of the SBUS devices or both can be a slave. When either of the SBUS devices is the master, only the 68040 can be the slave and the other SBUS device is idle. · Data Path. The chip controlling the communication Actel
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AC102 N631 n640 ac-102 n630 N638
Abstract: . The DCU write-data bus used to transfer data from the DCU to the PLB slave. Indicates the value of the , during a partial reconfiguration. Indicates a PLB slave acknowledges the current data-access request. Indicates the PLB slave is busy performing an operation requested by the DCU. Indicates an error was detected by the PLB slave during the transfer of data to or from the DCU. Indicates the DCU read-data bus contains valid data for transfer to the DCU. The DCU read-data bus used to transfer data from the PLB slave Xilinx
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C405XXXMACHINECHECK EICC405EXTINPUTIRQ PPC405 C405CPMCORESLEEPREQ C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ C405CPMTIMERRESETREQ
Abstract: Using Verilog HDL by Phil Rauba, Motorola Field Applications Engineer Purpose This article is intended to give a hardware engineer insight into the design methodology of using the Verilog Hardware , . The advantage of using an HDL, such as Verilog, is the ability to retarget the design to other , design was used to demonstrate the portability of the Verilog language, and included all of the circuits , state machine design technique and described using the Verilog Hardware Descriptive Language, with the Motorola
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MPA1000 dram verilog model MC68HC11RM verilog code to generate square wave motorola bubble memory controller pal spi verilog code 16 bit CISC CPU DL201
Abstract: The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI , lengths. SPI signals include the standard Serial Clock (SCLK), Master In Slave Out (MISO), Master Out Slave In (MOSI), bidirectional Serial Data (SDAT), and Slave Select (SS). When to Use the SPI Master Cypress Semiconductor
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verilog code for 8 bit fifo register
Abstract: -100 I2C-to-1-Wire line driver, software generation of 1-Wire waveforms with the PIC18F4550, and a Verilog , circuit board with a 1-Wire slave. A 1-Wire slave in a TO-92 or PR-35 package can directly be inserted at , port) 1-Wire Software code (PIC) or DS1WM (VHDL/Verilog, FPGA) I2C (PIC I2C port) 1-Wire PicoBlaze ASM code (FPGA) or DS1WM (VHDL/Verilog, FPGA) I2C I2CM* (VHDL, FPGA) TARGET SLAVE DEVICE , communication with Maxim's 1-WireM and I2C-based SHA-1 slave ICs. Multiple options are supported for host SHA Maxim Integrated Products
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74VHC1G125 74VHC1G125DF Apple Authentication coprocessor 74VHC1G14DF pin diagram of PIC18f4550 RS-232 to usb converter with pic18f4550 DS2460 XC3S400A DS2482-100 RS-232 XCF04S DS28E01/DS28CN01/DS2460
Abstract: networking protocols such as IP, TCP, UDP and ICMP providing wire speed services to Client applications , base addresses · 32-bit Avalon System Interface with separate slave ports for data and control , Accelerator MAC MII / SERDES Receive Interface Avalon Stream Slave Receive FIFO Receive , MII / SERDES Transmit Interface Avalon Stream Slave Control Avalon Slave Transmit FIFO , : Design Kit Overview Design and Simulation Language Optimized VHDL / Verilog or lower cost CPLD MorethanIP
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APEX20KE verilog code for mdio protocol vhdl code CRC32 802.3 CRC32 avalon vhdl vhdl code switch layer 2 vhdl code CRC 10/100/1000M 10000M IEEE802 10/100M MTIP-AVL-10
Abstract: Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire , PSoC CreatorTM Component Datasheet ® Serial Peripheral Interface (SPI) Slave 2.20 , any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a , the standard Serial Clock (SCLK), Master In Slave Out (MISO), Master Out Slave In (MOSI), bidirectional Serial Data (SDAT), and Slave Select (SS). When to Use the SPI Slave You can use the SPI Slave Cypress Semiconductor
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Abstract: slave receiver can read following a channel bonding sequence and still successfully align to that , ) Attribute CHAN_BOND_MODE Description STRING OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS OFF: No channel bonding , directly drives CHBONDI ports on one or more SLAVE_1_HOP transceivers. SLAVE_1_HOP: This transceiver is a slave for channel bonding. SLAVE_1_HOP's CHBONDI is directly driven by a MASTER transceiver CHBONDO port. SLAVE_1_HOP's CHBONDO port can directly drive CHBONDI ports on one or more SLAVE_2_HOPS transceivers Xilinx
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4x4 unsigned multiplier VERILOG coding 32x32 multiplier verilog code 12v relay interface with cpld in vhdl 80C31 instruction set adder xilinx national semiconductor catalog UG012 PCI64 DO-DI-PCI64-IP
Abstract: components. Using traditional design methods, you must manually write HDL modules to wire together the , generates either Verilog HDL or VHDL equally. In addition to its role as a system generation tool, SOPC , System Interconnect Fabric S DDR2 Memory SRC PIO (8-bit slave) Bus Bridge S DDR2 , Port S Avalon-MM Slave Port SRC Avalon-ST Source Port SNK Avalon-ST Sink Port A , modules and entities that you write using Verilog HDL or VHDL into SOPC builder as custom components. You Altera
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QII54001-10 Ethernet-MAC using vhdl UART using VHDL Builder microcontroller using vhdl vhdl code for ddr2
Abstract: the first four bits of the UFM slave address (bits A6-A3). It also provides the option to wire the remaining three slave address bits (A2 to A0) on the board. Instantiate the UFM Megafunction in the , high. The address of the slave is then sent on the SDA. Data transfer begins once the address is acknowledged by the slave. Data to be transmitted has to be held stable on the SDA line while the clock is , file do you want to create? Select from AHDL, VHDL, or Verilog HDL. What name do you want for Altera
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8 way dip switch AN-489 verilog code for i2c VHDL code for lcd interfacing to cpld 8-Way DIP Switch vhdl code for i2c Slave
Abstract: The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI , lengths. SPI signals include the standard Serial Clock (SCLK), Master In Slave Out (MISO), Master Out Slave In (MOSI), bidirectional Serial Data (SDAT), and Slave Select (SS). When to Use the SPI Master Cypress Semiconductor
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Abstract: . 15 Slave Interface , . 17 Single Master for Single Slave Implementation , . 18 Multiple Masters for a Single/Multiple Slave(s) Implementation , . 22 Appendix A â'" sBus Master Verilog Code , . 14 Figure 7: Single Master for a single sBus Slave Achronix Semiconductor
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UG047
Abstract: The SPI Master component provides an industry-standard 4-wire master SPI interface, as well as a 3-wire , SPI slave device. In addition to the standard 8-bit interface, the SPI Master supports a configurable , standard SCLK, MISO + MOSI (or SDAT) pins, and Slave Select (SS) signal generation. When to use the SPI , one or more SPI slave devices. In addition to "SPI slave" labeled devices, the SPI Master can be used with many devices implementing a shift register type interface. The SPI Slave component should be used Cypress Semiconductor
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0x1113
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